1. Field of the Invention.
The present invention relates to a complementary BiCMOS process and, more particularly, to a method for forming double-poly MOS and bipolar transistors with substantially identical device architectures.
2. Description of the Related Art.
Performance and manufacturability issues typically surround MOS and bipolar transistors which are formed with conventional BiCMOS processes due to the substantial differences that exist between the architectures of the MOS and bipolar devices.
FIGS. 1A and 1B show cross-sectional diagrams that illustrate the MOS and bipolar transistor architectures that result from using a conventional single-poly BiCMOS process. As shown in FIGS. 1A and 1B, one advantage of the single-poly process is that the gates of the MOS transistors and the emitters of the bipolar transistors are both formed from a single layer of polysilicon.
However, as further shown in FIGS. 1A and 1B, one significant disadvantage of the single-poly process is that when the single layer of polysilicon is etched to form the gates and emitters, the implanted base regions of the bipolar transistors can be significantly overetched. This, in turn, leads to leakage between the emitter and base regions.
The overetching occurs with this process because the implanted base regions are not protected by an etch stop, such as a layer of oxide, whereas the source and drain regions of the MOS transistors are normally protected by a layer of gate oxide during this step.
FIGS. 2A and 2B show cross-sectional diagrams that illustrate the MOS and bipolar transistor architectures that result from using a modified single-poly BiCMOS process. As shown in FIGS. 2A and 2B, the architecture of the MOS transistor remains the same while the architecture of the bipolar transistor incorporates a layer of oxide. The layer of oxide eliminates the overetching problem by forming an etch stop which protects the implanted base region.
The disadvantage of the modified bipolar architecture, however, is that a number of additional process steps are required to use and then remove the layer of oxide not covered by the emitter. In addition, the modified bipolar architecture typically requires a larger layout size.
In addition to using a single-poly architecture, high performance bipolar transistors generally require a double-poly architecture to enhance performance. FIGS. 3A and 3B show cross-sectional diagrams that illustrate the MOS and bipolar transistor architectures that result from using a conventional double-poly BiCMOS process.
As shown in FIGS. 3A and 3B, the architecture of the MOS transistor again remains the same while the architecture of the bipolar transistor incorporates two layers of polysilicon. As further shown, the double-poly process provides the same advantage as the conventional single-poly process, namely that the gates of the MOS transistors and the emitters of the bipolar transistors are both formed from a single layer of polysilicon (poly-2).
Another advantage of the double-poly process is that the layout size of the double-poly bipolar transistor is less than the layout size of the single-poly bipolar transistor. The layout size of the MOS transistor, however, remains the same.
Thus, there is a need for a BiCMOS process which eliminates the above-noted disadvantages, and also provides for a MOS transistor with a reduced layout size.